Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0823081
Kind Code:
A
Abstract:
PURPOSE: To provide a semiconductor device which is lessened in writing/erasing voltage and expanded in error writing margin and where a contact-less array directly connected to a memory cell is realized.
CONSTITUTION: A polysilicon film 22 serving as a floating gate and a polysilicon film 24 serving as a control gate are formed on a silicon substrate 11 by patterning, the source 17 of a MOS transistor is set lower enough than the drain 16 in impurity concentration. By this setup, a semiconductor device of this constitution can be protected against error writing and lessened in voltage required for writing/erasing.
Inventors:
MAARI KOUICHI
Application Number:
JP15688594A
Publication Date:
January 23, 1996
Filing Date:
July 08, 1994
Export Citation:
Assignee:
SONY CORP
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; H01L21/8247; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Fujiya Shiga (1 person outside)
Next Patent: BASIC CELL OF GATE ARRAY SEMICONDUCTOR DEVICE