PURPOSE: To eliminate unnecessary processing in a CPU and to improve processing speed in a computer constituted of plural processors by reducing the transmitting processing of the CPU at the time of writing data from a certain processor to a memory in the other processor and the frequency of CPU interruption generated at the time of receiving data.
CONSTITUTION: This inter-processor communication equipment is prepared for a computer consisting of plural processors and providing each processor with a memory. The inter-processor communication equipment is constituted of a receiver and transmitter. A CPU requests the transmitter to send a message. The transmitter divides a message into one or plural packets and transmits the message. Reception end interruption bits are set up in header parts of the message and respective packets so as to specify the generation of an interruption at the end of reception.
JPH03288951A | 1991-12-19 | |||
JPH0298246A | 1990-04-10 |