Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5935452
Kind Code:
A
Abstract:
PURPOSE:To reduce the variation of reference potential by forming a reference potential wiring at ground potential in two layer wirings, connecting a first wiring between them to a diffusion layer, using a second wiring as a wiring coating the whole surface of a chip-surface insulation and electrically connecting at least one point or more of these two wirings. CONSTITUTION:A source region 2 and a drain region 3 are diffused and formed to the surface layer section of a semiconductor substrate 1, the peripheries of these regions are surrounded by a field oxide film 6, and a gate electrode 5 buried in a gate insulating film 4 is set up to the surface of the substrate 1 between the regions 2 and 3. The whole surface is coated with the laminated film of insulating films 7 and 8, an opening is bored to these films, and a drain electrode 9 reaching the region 3 is formed surrounded by the film 7. A source electrode 10 reaching the region 2 is also set up, but the films 7 and 8 are penetrated by the electrode 10 at that time, and the whole surface containing an end section exposed is coated with a second wiring layer 11. Accordingly, a margin for input voltage is widened, and the generation of the malfunction of an internal circuit is avoided.
Inventors:
KOJIMA MICHIAKI
Application Number:
JP14635682A
Publication Date:
February 27, 1984
Filing Date:
August 24, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L23/52; H01L21/3205; (IPC1-7): H01L21/88
Attorney, Agent or Firm:
Uchihara Shin