PURPOSE: To decrease the disorder of the pipe line processing at the time of the branch instruction execution and to shorten the branch instruction execution time of the pipeline control data processor, by preserving the analysis results of the instruction of the cash memory.
CONSTITUTION: The instruction read out from the storage device is transferred from the interface circuit to the instruction control unit 2 and is latched to the register 10. The instruction of the register 10 is analyzed by the instruction decoder 11 and is transferred to the instruction execution unit. The cache memory 12 stores the instructon read out from the storage device and the control information analyzing the instruction with the instruction decoder 11. When the instruction is executed afte 2 time, the instruction is not analyzed and the program is executed by using the analysis results preserve in the cache memoery 12.
HASEGAWA ATSUSHI
AIMOTO TAKESHI
HITACHI MICROCUMPUTER ENG