PURPOSE: To relax the limit to memory access, by generating refresh address from a timing signal for instruction fetch and making refreshing with the refresh address.

CONSTITUTION: An instruction is read out from a program memory 2 receiving a timing signal for instruction fetch generated from a timing generator 1 is read out. This instruction is read out during fetch of a central processor 6. The timing signal generated during this fetch time is applied to a refresh counter 3 to count up the count value by one count and applied to a dynamic memory 4 to operate the addressing circuit, a dummy is read out with the count value of the counter 3 to produce refreshing. The accessing to the memory 4 can be attained independently of refreshing.