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Title:
TIMING SYNCHRONOUS CONTROLLER
Document Type and Number:
Japanese Patent JPS6020225
Kind Code:
A
Abstract:

PURPOSE: To prevent wastefullness by asynchronism by outputting timing signals from a reference clock pulse to plural devices and comparing the time-up signals with the admission signals from the calculator to stop all the control in case of incompleted conditions.

CONSTITUTION: A generalizing controller 11 controls the plant 12 by the reference clock in a timing synchronous controller 13 through each controller 1WN. A signal 01 is inputted from the controller into the synchronous controller 13; when a signal A from the calculator of the generalizing controller 11 is already there, a signal 11 is outputted; a signal T1 is immediately outputted as shown in the figure; the timing signals T2WT4 are outputted in successive delayed order. The signal I1 actuates a timer 201. Even when the timer 201 is time up, but if a generalizing signal B is not yet there, the signal I1' is not outputted; the following sequence is stopped and a signal I2' is outputted. When the signal I2' is outputted, a stop signal 800 is outputted in each controller 1WN, and at the same time stops the controller immediately, thereby allowing prevention of wastefulness of each equipment due to asynchronism.


Inventors:
MORIYAMA KUNIO
IBA DAIZOU
MATSUKI TSUTOMU
Application Number:
JP12793883A
Publication Date:
February 01, 1985
Filing Date:
July 15, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F1/06; G06F1/04; G21B1/00; G21B1/11; G21B1/25; (IPC1-7): G06F1/04; G21B1/00
Attorney, Agent or Firm:
Akio Takahashi