Title:
LOGIC GATE CIRCUIT
Document Type and Number:
Japanese Patent JPS5810927
Kind Code:
A
Abstract:
A Transistor-Transistor Logic (TTL) gate circuit is disclosed comprising an input transistor T1, an inverter transistor T2, an output transistor T3 and a pull-up transistor T4. When T2, T3 are non-conducting, VB appears at the output 12 and when T2, T3 are conducting, the output is substantially at earth. To achieve fast switching of T3 a different smaller amount of base current is applied to the inverter transistor T2 than is applied to the base of the output transistor T3. As shown, a current mirror circuit (T5, T6) can be used to control the amount of base current flowing between the input transistor (T1) collector terminal and the base terminal of the inverter transistor (T2). The mirror circuits limit the base current of T2 to an amount less than the base current that flows between the input transistor collector terminal and the base terminal of the output transistor T3. The value of R3 also limits the current though T2. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.
Inventors:
POORU MAIKERU SOROMON
JIIKUFURIIDO KURUTO BUIIDOMAN
JIIKUFURIIDO KURUTO BUIIDOMAN
Application Number:
JP8410082A
Publication Date:
January 21, 1983
Filing Date:
May 20, 1982
Export Citation:
Assignee:
IBM
International Classes:
H03K17/60; H03K19/00; H03K19/013; H03K19/088; (IPC1-7): H03K19/013; H03K19/088
Domestic Patent References:
| JPS5367341A | 1978-06-15 |
Attorney, Agent or Firm:
Tsukio Okada