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Title:
ADDRESS BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS605492
Kind Code:
A
Abstract:

PURPOSE: To eliminate the effects of the phase difference of input signals and the noises without increasing the number of external signal terminals, by obtaining an OR of the pulse signal every address input terminal to produce the trigger signal for a piece of address latch circuit and to input the trigger signal to a trigger input terminal of each address latch circuit.

CONSTITUTION: A circuit group 7 is provided to each address input terminal, and an AO address input terminal 17 is connected to the input terminal of the 1st circuit group 7. At the same time, the A1 and A2 address input terminals 18 and 19 are connected to the input terminals of the 2nd and 3rd circuit groups 7 respectively. A wired OR4 is obtained among output terminals 8W11 of the 1stW 4th circuit groups 7, and the output terminal of the OR4 is connected to a trigger input terminal. The group 7 detects the changing point of an address input signal to produce a trigger signal 12 which fetches the address information to an address latch circuit 6. Then the data input signal of the circuit 6 is fetched to the address latch circuit by the signal 12.


Inventors:
HANDA HIROMITSU
Application Number:
JP11090383A
Publication Date:
January 12, 1985
Filing Date:
June 22, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/41; G11C11/34; G11C11/413; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Akio Takahashi



 
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