PURPOSE: To prevent a frequency dividing circuit from being reset erroneously, by controlling a power-on clear output for resetting the frequency dividing circuit in power-on operation through a gate which responds to the state of a load switch.

CONSTITUTION: The rising of a power-on clearing circuit 9 is delayed in power- on operation by a resistane R1, capacitor C1, etc., and a high level output passed through an inverter G1 resets an FF group 2 for frequency division in the delay period through an AND gate G2 opened by the high level output of an inverter G3. In this state, an alarm switch 7 is closed at alarm time to supply a current to a load such as a lamp 8, and then the output of the inverter G3 is inverted to a low level to close the gate G2. Therefore, even if the power voltage drops owing to the feeding to the lamp 8 to invert the output of the inverter G1 to the high level, this high-level output is cut off and the FF group 2 is prevented from being reset erroneously.