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Patent Searching and Data


Title:
BALANCED FEEDING CIRCUIT
Document Type and Number:
Japanese Patent JPS585076
Kind Code:
A
Abstract:

PURPOSE: To obtain an inexpensive, small-sized balanced feeding circuit for feeding a telephone set, by composing the feeding circuit only of a DC bias circuit with high resistance and a couple of current limiting circuits.

CONSTITUTION: A DC voltage source 1 supplies a 0V voltage to a terminal 1c, a positive voltage to a terminal 1a, and a negative voltage to a terminal 1b. The 1st and 2nd current limiting circuits 11 and 31 conduct constant currents without reference to voltage drops across the circuits. When a telephone set is connected between output terminals 2a and 2b, currents determined by the 1st and 2nd current limiting circuits 11 and 31 flow to the telephone set and a balance circuit 7. At this time, if a current difference is generated between the 1st and 2nd current limiting circuits 11 and 31, the difference current flows through the resistors 5a and 6a of the balance circuit 7 and the potentials at the output terminals 2a and 2b are held approximately at the voltage at the terminal 1c.


Inventors:
HISHINUMA ESAO
Application Number:
JP10305981A
Publication Date:
January 12, 1983
Filing Date:
July 01, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04M19/00; (IPC1-7): H04M19/00
Attorney, Agent or Firm:
Uchihara Shin