Title:
【発明の名称】デ―タパルスの高速連続直列流を再構成アナログ信号に変換する変換回路
Document Type and Number:
Japanese Patent JP2542606
Kind Code:
B2
Abstract:
A serial-to-parallel converter receiving a clock signal and continuous serial stream of input data, each having TTL logic levels, produces parallel outputs for driving current switches of a digital-to-analog converter (DAC). The data and clock signals each are converted to ECL logic levels by a pair of emitter-coupled differential lateral PNP transistors having their collectors coupled to a pair of NPN current mirror circuits, the outputs of which drive the bases and emitters of a pair of NPN emitter follower transistors, resulting in very high bandwidth operation. Master-slave ECL shift register bit outputs are directly coupled, without emitter followers, to ECL inputs of output latches that drive the DAC current switches, resulting in substantially reduced power consumption and chip area. Saturation of the emitter-coupled NPN transistors of the latch circuit is avoided by providing an upper supply voltage level for the load resistors of the master-slave shift register bits that is one diode drop lower than the upper supply voltage level for the load resistors of the latch circuit. A unique ECL one-shot circuit responds to an external latch enable control signal having TTL logic levels to produce internal complementary ECL enable signals that enable the output latches.
Inventors:
FUREDERITSUKU JEI HAITON
Application Number:
JP3130787A
Publication Date:
October 09, 1996
Filing Date:
February 13, 1987
Export Citation:
Assignee:
BURR BROWN CORP
International Classes:
H03M1/66; H03K3/2885; H03K3/289; H03K19/018; H03K19/0185; H03M1/74; H03M9/00; (IPC1-7): H03K19/018; H03M1/74; H03M9/00
Domestic Patent References:
| JP60241328A | ||||
| JP59178689A | ||||
| JP60152128A |
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)