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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5913361
Kind Code:
A
Abstract:

PURPOSE: To obtain the integrated circuit device of small temperature dependency by forming a resistance element consisting of a metallic oxide film or a metallic film connected to a buried layer in concentration higher than an epitaxial layer through a first layer.

CONSTITUTION: The n+ buried layer 11 is formed selectively to a p type silicon substrate 5 before forming the n type epitaxial layer 2, and two n+ diffusion layers 12 in high concentration and a p type diffusion layer 3 formed at the same time as the diffusion of the base of an npn transistor are formed selectively so as to reach the n+ buried layer 11 from the mutually isolated surfaces of the epitaxial layer 2 in order to reduce an effect of a bulk resistor in the epitaxial layer 2 having an effect on the resistance element formed by the n+ buried layer 11 in parallel as much as possible. Thin-film resistors, which are formed through the evaporation, etc. of Ta, etc. and one ends thereof are connected to the buried layer 11 through metallic layers 6 and the n+ diffusion layers 12, are formed on a protective film 12.


Inventors:
JINMON MASASHI
Application Number:
JP12421182A
Publication Date:
January 24, 1984
Filing Date:
July 14, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/822; H01L27/04; (IPC1-7): H01L27/04
Domestic Patent References:
JPS503793A1975-01-16
JPS51102586A1976-09-10
Attorney, Agent or Firm:
Shinichi Kusano



 
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