PURPOSE: To improve the processing ability of a CPU by providing a main storage device and a storage section for data transfer to a memory control section and making the memory access to the main storage device from the CPU independently of the data transfer to relieve the load to the main storage device.

CONSTITUTION: A data transfer system consists of the central processing unit CPU1, the main storage device MEM4, a memory control section MCU3 and plural channel device 2. A command address word CAW is stored to the MEM4 and the data transfer storage section TBF5 designated by a data address section of the CAW is connected to the MCU3. The CPU1 executes an input instruction to an input/output device A, the device 2 reads the CAW of the MEM4, reads the data transfer destination from the TBF5 according to the address and transfers the data to other input/output device B. Then the load to the MEM4 is relieved to improve the processing capability of the CPU1.