PURPOSE: To simplify a circuit and to reduce a read access time by using a dynamic RAM not attended with a refresh function at data read as a data bus memory.

CONSTITUTION: A control signal WE commanding write/read and an n-bit address input A are led to the input of a read/write selection circuit RW, the output of the selection circuit RW is led to the input of a memory cell CELL so as to attain write/read operation to the memory cell CELL. In applying a write signal to a write data line WD at the write operation and applying a voltage to a write selection line in the memory cell CELL, a transistor (TR) Q1 is turned on and a capacitor C is charged according to the potential of the write signal. In applying a voltage to a read selection line R and a read data line RD at read operation, a TRQ3 is turned on and the stored data is read to the read selection line RD via a TRQ2 turned on/off by the electric charge stored in the capacitor C.