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Title:
SAMPLING CONTROLLER
Document Type and Number:
Japanese Patent JPS6033609
Kind Code:
A
Abstract:
PURPOSE:To set optionally the period of switching between a control operation mode and a holding mode with a program by calculating the deviation between the correction output from a digital operating circuit and the current output of an integrating circuit and inputting this deviation value to the input of the integrating circuit only in the holding mode. CONSTITUTION:In the control operation mode, a CPU11 calculates a proportional term and a term to be integrated at every sampling timing and converts them in a D/A converter 14 and outputs them while switching them in a multiplexer 15, and they are amplified by holding amplifiers 16 and 17, and the term to be integrated is integrated by a means 19, and the proportional term is subjected to differential addition by a differential adding circuit 18 and is added to the integral value, and the addition result is outputted to an output 21. Thus, the proportional plus integral differential PID operation is performed. When the time of the holding mode comes, the CPU11 outputs preceding stored contents to lead out the correction output to a holding amplifier 25 through the converter 14 and the multiplexer 15. A differential amplifier outputs the deviation between the correction output and the current output, and an analog switch 27 is turned on to give it to the integrating circuit 19. When the output of the circuit 19 reaches the correction output, the output is stabilized.

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Inventors:
KANOU IKUO
KITAGAWA SHINICHI
Application Number:
JP14317283A
Publication Date:
February 21, 1985
Filing Date:
August 04, 1983
Export Citation:
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Assignee:
SHIMADZU CORP
International Classes:
G05B7/02; G05B21/02; (IPC1-7): G05B21/02
Attorney, Agent or Firm:
Nakamura Shigenobu