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Title:
STEREO DEMODULATING CIRCUIT
Document Type and Number:
Japanese Patent JPS6021646
Kind Code:
A
Abstract:

PURPOSE: To simplify the elimination of noise by using an output signal of a level control circuit as a switching signal used for a stereo demodulating circuit.

CONSTITUTION: A 228kHz signal in synchronization with a stereo pilot signal is frequency-divided and 114kHz and 38kHz rectangular wave signals are generated respectively from the 1st frequency divider 10 and the 2nd frequency divider 12. Switches 14, 15 are controlled by the 38kHz signal of positive and opposite phases and their outputs are supplied to the 1st and 2nd level control circuits 16, 17. Signals whose phases are opposite to each other obtained at the 1st and 2nd output terminals 23, 24 are applied to a difference signal circuit as switching signals to attain demodulation.


Inventors:
TANAKA KANJI
Application Number:
JP12992583A
Publication Date:
February 04, 1985
Filing Date:
July 15, 1983
Export Citation:
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Assignee:
SANYO ELECTRIC CO
TOKYO SANYO ELECTRIC CO
International Classes:
H04B1/16; H04H20/47; H04H40/72; H04H1/00; (IPC1-7): H04H5/00
Attorney, Agent or Firm:
Takuji Nishino



 
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