PURPOSE: To improve the memory use efficiency to make high-speed processings possible by providing an address generating part, a control part, and a data buffer part and combining bit data to write data in a memory in word data units.

CONSTITUTION: When write data is inputted after initial values are set to individual registers in an address generating part 100, the generating part 100 outputs a part indicating an access bit address to a control part 200 and a data buffer part 300 synchronously with this input. In the buffer part 300, a shift operation is performed through a multiplexer 304 by the input of a shift control signal, and data in a word unit is outputted from a data register 302 to the memory. Input data is decided through a decision circuit 201 and etc. by the control part 200 to perform the write control to the memory. Since the memory is accessed after gathering data to a word unit in the memory write processing of bit data in this manner, the memory use efficiency is improved, and data processings are performed in a high speed.