【発明の名称】D形フリップフロップを使用した分周回路

Japanese Patent JPH0691425

B2

PURPOSE:To attain high speed circuit with less delay quantity by providing a selector selecting information read or self-output read in a form of a control signal at an FF input terminal of a sequence circuit using a D type FF and inputting directly a clock to a clock terminal. CONSTITUTION:Information is given to an AND circuit 5 of a selector 2, and a timing generating circuit 3 gives specific bit information A to a D FF 1 with a delay of a time t1 from a point D of a signal CLK to generate an H level pulse and to input it to an AND circuit 5 of the selector 2 and an inverted AND circuit 4. The information A enters the FF 1 via the AND circuit 5 and an OR circuit 6, segmented by the CLK at a point E, the bit information A is outputted and the output of the circuit 3 goes to 'L', and it is given to the FF 1 via the input inverted AND circuit 4 and the OR circuit 6 of the selector and the information A is held. The delay quantity is only a delay t2 of the FF 1 only from a point E of the CLK and high speed operation is attained. Moreover, no delay quantity is stored.

Yuichi Sato

JP8850987A

November 14, 1994

April 10, 1987

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富士通株式会社

H03K23/00; H03K3/037; H03K23/40; H03K23/50; (IPC1-7): H03K3/037; H03K23/00; H03K23/40

JP4929756A
JP4944655A
JP52120665A
JP49147952U

Koshiro Matsuoka

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