PURPOSE: To reduce a circuit scale by providing a means detecting a frequency of an input clock and a frequency divider means whose frequency division ratio is freely changed depending on the detected frequency to the subordinate clock generating circuit.
CONSTITUTION: A line clock 1 is inputted to a frequency divider 4 and a frequency detector 2. When frequencies fn of the clock 1 are two kinds such as f1, f2 (f1>f2), a time constant of a one-shot multivibrator HMV2 is set between 1/f1 and 1/f2. When the clock frequency is f2 the output of the MHV is set to an H level so that the MMV2 is set to the retrigger state. On the other hand, when the clock frequency is f1, since the MMV2 does not reach the retrigger state, the output of the MMV is a one-shot output. A control circuit 3 detects the MMV output to control the frequency division ratio of the frequency divider 4. That is, the frequency division ratio of the frequency divider 4 is decided so that the frequency of the frequency division output 5 is the same f0 with respect to the clock frequencies f1, f2.
DOUMORI NORITOSHI
OKI TAIJI
| JPH06140920A | 1994-05-20 |