Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6054455
Kind Code:
A
Abstract:
PURPOSE:To perform a normal connection by providing an insulating film on the side wall of a hole for exposing the connected portion of a lower layer element through an upper layer element by utilizing an anisotropic etching technique, and superposing a wiring metal layer. CONSTITUTION:An insulating film 6 is formed on an upper layer element 2, the connecting portion 4 of a lower layer element 1 is exposed by a normal method on an open portion 10, and the connecting portion 5 of the upper layer element 2 is exposed with an open portion 11. Then, insulating films 13 are formed over the inner walls and the bottoms of the holes 10, 11 from the upper surface of the film 6, the films 13 are allowed to remain only on the inner walls of the holes 10, 11 by reactive ion etching, and holes 14, 15 which are exposed with the portions 4, 5 are formed. Subsequently, wiring metal 16 is covered, a resist mask 17 is covered, a wiring pattern is formed, the mask is removed, and the desired connection is completed. According to this structure, the function of the upper layer element due to the contact of the upper layer with the wiring layer is not failed.
Inventors:
ITAKURA HIDEAKI
YONEDA MASAHIRO
INUISHI MASAHIDE
YONEDA MASAHIRO
INUISHI MASAHIDE
Application Number:
JP16436383A
Publication Date:
March 28, 1985
Filing Date:
September 05, 1983
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/00; H01L21/3213; H01L21/60; (IPC1-7): H01L27/00
Domestic Patent References:
| JPS57121253A | 1982-07-28 | |||
| JPS5112507A | 1976-01-31 |
Attorney, Agent or Firm:
Masuo Oiwa