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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5821366
Kind Code:
A
Abstract:

PURPOSE: To contrive to optimize the characteristics of three elements by forming the base of the third element by overlapping the impurity distribution of the bases of severally independent first and second elements in the IC consisting of vertical transistors having three kinds or more of different structure.

CONSTITUTION: Island layers 20, 22, 24 are formed by surrounding an N epitaxial layer on a P type Si substrate by N+ buried layers and P+ isolating layers. The buried layers are extracted to the surface by deep N+ layers, P- bases 32, 34 (concentration distribution a1=a2) are shaped, and a P type external base 36, an injector 38 and P bases 40, 42 (concentration distribution b1>a1, a2, b2=b1) are molded at the same time. Accordingly, concentration distribution C=a2+b2 is formed in the island 24. The N+ layers 44, 46 48 of distribution d1∼d3 are shaped at the same time. According to this constitution, the base of the I2L of the island 20 has low concentration and is deep, the base of the high-frequency element of the island 22 has high surface ocncentration and is shallow, and the base of the high dielectric-resistance element of the island 24 is the sum of both distribution, and the IC in which hfe of the I2L, the cut-off frequency of the high-frequency element, and the punch through voltage BVCEO of the high dielectric-resistanc element are kept properly is obtained.


Inventors:
KANZAKI KOUICHI
Application Number:
JP11977081A
Publication Date:
February 08, 1983
Filing Date:
July 30, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8226; H01L21/331; H01L27/02; H01L27/082; H01L29/73; (IPC1-7): H01L27/08; H01L29/72
Attorney, Agent or Firm:
Takehiko Suzue