PURPOSE: To correctly operate a memory even at the restoration from power failure without changing the construction of a CPU and the memory to non- volatility, by providing a specific address detection circuit, a designated address setter, and a power switch outputting a designated address data alternate.

CONSTITUTION: When a CPU1 receives a reset signal at the application of power supply, data of FFFF address is outputted. This specific address (FFFF) data is detected at a specific address detection circuit 7 and a signal is applied to an electronic switch 4. Although the electronic switch 4 outputs the data on a normal address bus 3 to an address bus 5 while connecting both buses, a signal from the circuit 7 connects address buses 9 and 5 to output the OFFF address data in an area 22 stored with a designated address setter 8 to the bus 5. Thus, the OFFF address in the non-volatile memory area 22 is designated.