Title:
TESTING METHOD OF SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS6021536
Kind Code:
A
Abstract:
PURPOSE:To largely curtail the wafer processing time for discriminating element characteristic by retrieving position and direction of good-bad elements boundary line from good-bad distribution of elements within one block, and sequentially shifting the element block to be measured next along the good-bad elements boundary on the basis of such result. CONSTITUTION:The block B2 is the good-bad elements generating pattern where central two elements are good, two elements in the right side are good, two elements in the left side are bad, and a part of boundary line L crossing the block B2 is retrieved from this good-bad elements generating patterns and is then stored. Since the good-bad element generating pattern of block B2 is in the Y axis direction, the block is shifted for three lines in the direction of Y axis, since the central element 2 of block B3 is bad, it is then shifted as long as one element to the right in order to measure the block B4. The blocks are shifted sequentially along the boundary line L so that the central elements of measuring block becomes good and thereby the boundary line L is obtained.
Inventors:
ICHII TOYOICHI
Application Number:
JP12988783A
Publication Date:
February 02, 1985
Filing Date:
July 15, 1983
Export Citation:
Assignee:
KANSAI NIPPON ELECTRIC
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Shogo Ehara
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