PURPOSE: To reduce the area of a row decoder and the area of wires, to decrease the size and cost of a chip and to further increase the capacity of the chip by the minimum size of a memory cell without altering the manufacturing steps of an integrated circuit in a selector of the memory cell.

CONSTITUTION: A row decoder circuit is composed of a P-channel MOS transistor 30 forming an NAND gate with phase inverted timing signals 29, 31, phase inverted address inputs 200, 300 and address inputs 301∼30m, similarly N-channel MOS transistors 331∼33m, P-channel MOS transistors 35, 36, 39 forming an NOR gate, N-channel MOS transistors 37, 40, and output terminals 38, 41 of the NOR circuit. The MOS transistor which forms the NOR gate and is connected to the output of the NAND gate is one, thereby remarkably simplifying the wire, and the N-channel MOS transistors 37, 40 which are operated by the timing signal are disposed through memory cell array, thereby further simplifying the wire.