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Title:
PULL-IN DETECTION SYSTEM OF PLL CIRCUIT
Document Type and Number:
Japanese Patent JPS6019325
Kind Code:
A
Abstract:

PURPOSE: To simplify the detecting circuit by constituting a low pass filter of a PLL circuit as an active filter comprising an operational amplifier and detecting whether or not its output voltage is within a voltage range being a power supply voltage or below and a zero voltage or over of the operational amplifier so as to detect the pull-in state.

CONSTITUTION: In constituting the PLL circuit through the use of a frequency phase comparator 1, the pull-in range is the entire range oscillated by a voltage controlled oscillator (VCO) and limited by the power voltage of the operational amplifier constituting the low pass filter (LPF) actually. The normal frequency phase comparator and the LPF are shown in Fig. A and the relation between the LPF output voltage and the VCO output frequency is shown in Fig. B. In Fig. B, a lower limit voltage V1 is zero (ground potential) and an upper limit voltage V2 is a power supply voltage (Vcc) of the operational amplifier, and when the output of the PLL circuit is pulled in by the fo, an Edc becomes Vo. Thus, the pull-in state of the PLL circuit is detected by detecting the DC voltage range of V1∼V2.


Inventors:
KOBAYASHI MASUO
Application Number:
JP12730883A
Publication Date:
January 31, 1985
Filing Date:
July 13, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03L7/095; (IPC1-7): H03L7/08
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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