PURPOSE: To stably and precisely extract clock pulses by gating the clock pulses by a multiple pulse width output signal from a multiple pulse width generating circuit to extract the optional number of clock pulses.

CONSTITUTION: JK-flip flops (FFs) 1, 2 to be triggered by the trailing edge of a clock pulse in response to a synchronous or asynchronous input pulse constitute a synchronous circuit for generating synchronous pulses having the pulse width of one cycle length. A D-FF 4 and OR gates 5, 6, 7 to be triggered by the trailing edge of a clock pulse constitute a multiple pulse generating circuit for generating clock pulse extracting pulses having the pulse width of the optional multiple of a synchronous pulse. AND gates 8, 9, 10 constitute a gate circuit for gating the optional number of clock pulses by an output from the multiple pulse generating circuit.