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Patent Searching and Data


Title:
ERROR CORRECTING DECODER
Document Type and Number:
Japanese Patent JPS5912646
Kind Code:
A
Abstract:

PURPOSE: To improve the correcting ability of a titled recorder, by allocating a zero digital code to a symbol not transmitted, in an error correcting decoder performing a soft decision.

CONSTITUTION: A receiving signal from input terminals 100', 101' is compared with a threshold value by comparators 51∼54, and 55∼58 of a soft decision circuit 60 and used as an address of memories 61, 62. An output of the circuit 60 is calculated for the correlation with each transmission pattern by adders 30'∼33'. The output of the adders 30'∼33' is inputted to a processor 40' and a discriminating output is obtained from a terminal 102' based on the Viterbi algorithm. Since the 0 of the discrimination output is a so-called zero digital code, the zero digital code is assigned to a symbol not transmitted actually.


Inventors:
YASUDA YUTAKA
FURUYA YUKITSUNA
MURAKAMI SHIYUUJI
NAKAMURA KATSUHIRO
Application Number:
JP12094782A
Publication Date:
January 23, 1984
Filing Date:
July 12, 1982
Export Citation:
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Assignee:
KOKUSAI DENSHIN DENWA CO LTD
NIPPON ELECTRIC CO
International Classes:
H03M13/23; H04L25/06; (IPC1-7): H04L1/10
Attorney, Agent or Firm:
Uchihara Shin