Title:
MEMORY SYSTEM
Document Type and Number:
Japanese Patent JPS5823376
Kind Code:
A
Abstract:
The efficient promotion of data from a backing store (disk storage apparatus 16-18 termed DASD) to a random access cache 40 in a storage system such as used for swap and paging data transfers. When a sequential access indicator (SEQ in 22) is sent to and retained in the storage system, all data specified in a subsequent read «paging mode» command is fetched to the cache from DASD. If such prefetched data is replaced from cache and the sequential bit is on, a subsequent host access request for such data causes all related data not yet read to be promoted to cache. A maximal amount only of related data may be promoted; such maximal amount is determined by cache addressing characteristics and DASD access delay boundaries. Without the sequential bit on, only the addressed data block is promoted to cache.
Inventors:
DEEBITSUDO GOODON RIIDO
RICHIYAADO EDOWAADO RIIKU
JIYON SUTEIIBUN UIRIAMUZU
JIYON HANTO KURISUCHIYAN
MAIKERU HAWAADO HAATANGU
AASAA HAABAATO NORUTA
RICHIYAADO EDOWAADO RIIKU
JIYON SUTEIIBUN UIRIAMUZU
JIYON HANTO KURISUCHIYAN
MAIKERU HAWAADO HAATANGU
AASAA HAABAATO NORUTA
Application Number:
JP10148782A
Publication Date:
February 12, 1983
Filing Date:
June 15, 1982
Export Citation:
Assignee:
IBM
International Classes:
G06F12/08; (IPC1-7): G06F13/00; G11C9/06
Domestic Patent References:
| JPS5680872A | 1981-07-02 | |||
| JPS5054249A | 1975-05-13 | |||
| JPS5444176A | 1979-04-07 |
Attorney, Agent or Firm:
Koichi Tonmiya