Title:
MANUFACTURE OF SEMICONDUCTOR MULTILAYER INTERCONNECTION
Document Type and Number:
Japanese Patent JPS6028246
Kind Code:
A
Abstract:
PURPOSE:To taper the side wall of through-hole, and to obtain smoothed multilayer interconnection structure by executing anisotropic etching while using a resist film as a mask and completing the hole through isotropic etching, when a first Al wiring layer having a predetermined shaped is formed on a semiconductor substrate, the first Al wiring layer is coated with an inter-layer insulating film and the through-hole for applying a second Al wiring is bored. CONSTITUTION:The surface of a Si substrate 1 is coated with a SiO2 film 2, first layer wirings 3 consisting of Al-Si having predetermined shapes are formed on the film 2, and an inter-layer SiO2 film 4 in approximately 8,000Angstrom thickness is shapeed on the whole surface containing the wirings 3 through a CVD method. Through-holes 5 are bored to the film 4 through etching while using a resist film having windows positioned on the wirings 3 as a mask, but the films 4 are left only by approximately 2,000Angstrom thickness on the bottoms and upper sections are removed through anisotropic etching at that time. The films 4 remaining on the bottoms are removed through isotropic etching, and th holes 5, upper edge sections thereof have tapers 5a, are obtained. A similar second layer wiring 6 being in contact with the wiring layers 3 are attached thereto by utilizing the holes.
Inventors:
MATSUI HIROSHI
Application Number:
JP13523583A
Publication Date:
February 13, 1985
Filing Date:
July 26, 1983
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/3205; H01L21/302; H01L21/3065; (IPC1-7): H01L21/302
Attorney, Agent or Firm:
Hiroshi Kikuchi