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Title:
DATA DISCRIMINATING CIRCUIT
Document Type and Number:
Japanese Patent JPS5942621
Kind Code:
A
Abstract:

PURPOSE: To prevent the drop of a phase margin of a read-out data even in case when a large instantaneous variation occurs when inputting a data, by extending two windows so that a part of them is overlapped to each other, and also constituting so that only its one is selected in case when one data input is set to both of two data discriminating circuits.

CONSTITUTION: In case when a variation of an input is very large, when both a signal D0W and D1W are "1", two of an FF9 and 10 are set simultaneously due to a data input, but a normal data output is obtained by a data discriminating circuit 11. That is to say, in case when a signal AB is "0", it is made to pass through an NAND circuit 12 and an OR circuit 14, and on the other hand, in case when a signal CD is "0", it is inputted to an FF15 through an NAND circuit 13 and the OR circuit 14, and a data output is obtained by a VCO output signal. Thereafter, by this data output, the FF9 is reset, and the FF10 is reset through an OR circuit 8. A period of the data input, a period T of the VCO output, and pulse width TW of the signal AB and CD are equal, respectively, and extended data discriminating window width becomes pulse width TW+ΔTW of the signal D0W and D1W.


Inventors:
HORIE TSUNEO
ICHIBA TADAYUKI
TAKEUCHI TAKIKAZU
Application Number:
JP15364382A
Publication Date:
March 09, 1984
Filing Date:
September 03, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11B20/14; G11B20/10; (IPC1-7): G11B5/09
Attorney, Agent or Firm:
Masatoshi Isomura



 
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