PURPOSE: To obtain a processor unit having both functions of operation and numeral generation with a same hardware by providing said unit with a multiplexer switching a bus from an input latch and the one from an output latch.

CONSTITUTION: External data are inputted to the input latch 1 from a queue memory 6 and latched by a clock pulse 21. An operation part 2 to execute logical operation or arithmetic operation executes the operation by using output data from the input latch 1 and that from the multiplexer 5. The input of the multiplexer 5 is supplied from the input latch 1 and the output latch 3. While referring a part of the data from the input latch 1, a control part 4 switches the multiplexer 5. In case of logical operation or arithmetic operation, the data from the input latch 1 are selected as the output of the multiplexer 5, and at the generation of a numeral, the data from the output latch 3 are selected by a control signal 18.