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Patent Searching and Data


Title:
MEMORY CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS5916060
Kind Code:
A
Abstract:

PURPOSE: To suppress the repetition of the same data in a memory, by using a count end detecting circuit and detecting the counted value of data bits of an address pointer, and suppressing the counted signal of the pointer.

CONSTITUTION: When data is read out of an address of a memory device A, such contents that the output of the address pointer B incidates an optional address are set, and then data corresponding to the address is outputted from the device A and set in a latch circuit C. This data is set as a counted value in a counter circuit E to decide on how many times the data is repeated, and the result is inputted to the timing controlling circuit of the pointer B. This timing controlling circuit suppresses the increment of the pointer by N times when the data is repeated by N times, so the data of a data bus output same data by N times.


Inventors:
TOYOFUKU TAKASHI
Application Number:
JP12388882A
Publication Date:
January 27, 1984
Filing Date:
July 16, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C7/00; G06F12/04; G06F13/00; (IPC1-7): G11C7/00
Attorney, Agent or Firm:
Uchihara Shin