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Patent Searching and Data


Title:
ATM SWITCH OVERLOAD TEST EQUIPMENT
Document Type and Number:
Japanese Patent JPH0730552
Kind Code:
A
Abstract:

PURPOSE: To make the size of the hardware scale small by copying a primitive load cell generated from a primitive load cell generating circuit by input port number of a tested ATM switch and giving routing information to the header so as to form a load cell.

CONSTITUTION: A primitive load cell generating circuit 1 generates a primitive load cell 6 as a test cell and a copy circuit 2 copies the primitive load cell 6 corresponding to an input port of an ATM switch 5. Then a routing load circuit 3 designates the share destination to the ATM switch in the unit of input ports for the primitive load cell 6 to provide an output of a load cell 7 with header information given thereto to the ATM switch 5. Then an output timing of the load cell 7 outputted from the ATM excess load test control voltage 4 is set by a test cell generation control section 8 based on test pattern information 9. The control section 8 sets the frequency of occurrence of the primitive load cell 6 generated by the circuit 1, number of outputs from the copy circuit 3 and content of header information.


Inventors:
HAMAKAWA YASUHISA
SUZUKI KOJI
TAKAGI KOJI
OSHIMA HITOSHI
OKAMOTO YASUSHI
KATAKURA HITOSHI
Application Number:
JP17332793A
Publication Date:
January 31, 1995
Filing Date:
July 13, 1993
Export Citation:
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Assignee:
NEC CORP
NIPPON TELEGRAPH & TELEPHONE
HITACHI LTD
OKI ELECTRIC IND CO LTD
FUJITSU LTD
International Classes:
H04Q3/00; H04L12/26; H04L12/28; (IPC1-7): H04L12/28; H04L12/26; H04Q3/00
Domestic Patent References:
JPH0583291A1993-04-02
JPH0371750A1991-03-27
JPH05136814A1993-06-01
Attorney, Agent or Firm:
Naotaka Ide