Title:
【発明の名称】論理回路の遅延時間改良方式
Document Type and Number:
Japanese Patent JP2871968
Kind Code:
B2
Abstract:
PURPOSE:To improve the delay time without changing logic and to easily perform static delay analysis by preparing a new function block from the route information of a delay analysis result to be outputted from the delay analysis means. CONSTITUTION:A new function block preparing means 5 changes a flip-flop which corresponds to the start point of a critical pulse into a latch based on the delay analysis result stored in a delay analysis means 3 and function block information stored in a function block information storage means 4, further it prepares a new block having the function equivalent to the function block constituting the route of the critical path, adding it to the means 4. A logic circuit correction means 6 inputs the information of the logic circuit stored in a logic circuit information storage means 1, the information of the function block stored in the means 4, and the delay analysis result stored in the means 3, changes the information of the logic circuit to the logic circuit using the new function block, outputting it to the means 1.
Inventors:
KUROHASHI MANABU
Application Number:
JP22113592A
Publication Date:
March 17, 1999
Filing Date:
August 20, 1992
Export Citation:
Assignee:
HOKURIKU NIPPON DENKI SOFUTOEA KK
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP63280301A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)