Title:
【発明の名称】低欠陥ポリシリコン集積回路の製造方法
Document Type and Number:
Japanese Patent JP2520990
Kind Code:
B2
Abstract:
A method of removing natural oxides and other contaminants on silicon or polysilicon and then depositing polysilicon thereon. The natural oxide is substantially removed from the exposed silicon with an anhydrous etchant and then the polysilicon is deposited on the exposed silicon. The etching and depositing steps occur in the same reactor chamber (in-situ). A portion of the end of the selective etching step overlaps with a portion of the beginning of the polysilicon deposition step to achieve an interface between the underlying silicon and the deposited polysilicon that is substantially free of native oxides and other contaminants.
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Inventors:
ANATORII FUEIGENSON
CHANNKUEI FUAN
CHANNKUEI FUAN
Application Number:
JP10514491A
Publication Date:
July 31, 1996
Filing Date:
April 11, 1991
Export Citation:
Assignee:
EI TEI ANDO TEI CORP
International Classes:
H01L21/205; H01L21/285; H01L21/302; H01L21/304; H01L21/306; H01L21/3065; H01L21/311; H01L21/321; (IPC1-7): H01L21/205; H01L21/304; H01L21/306; H01L21/3065
Domestic Patent References:
| JP6379392A | ||||
| JP1257192A |
Attorney, Agent or Firm:
Hirofumi Mimata