Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2516429
Kind Code:
B2
Abstract:
PURPOSE:To form channel stoppers between gate electrodes although the gate electrodes are highly integrated, by a method wherein, after the surface of a substrate between insulating layers formed on the side surfaces of electrodes is etched and impurity is eliminated, thereby second layer gate electrodes are formed. CONSTITUTION:Impurity 6 for channel stoppers is implanted in the surface of a semiconductor substrate 1 between first layer gate electrodes 5. Thus the implantation can be easily performed. After the implantation, insulating layers 7 are formed on the side surfaces of the first layer gate electrodes 5; the surface of a semiconductor substrate 1 between the insulating layers 7 is etched, and impurity 6 in the semiconductor substrate is eliminated; impurity is left only under the insulating layer 7; second layer gate electrodes 9 are formed on the surface of the semiconductor substrate 1 between the insulating layers. That is, the impurity 6 in the semiconductor substrate under the insulating layers 7 serves as channel stoppers. Thereby the channel stoppers can be formed between gate electrodes in a self-alignment manner, although the gate electrodes are highly integrated.
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Inventors:
FUJIMOTO KOJI
OOSHIMA MASATOSHI
OOSHIMA MASATOSHI
Application Number:
JP11706189A
Publication Date:
July 24, 1996
Filing Date:
May 10, 1989
Export Citation:
Assignee:
SHARP KK
International Classes:
H01L21/76; H01L21/336; H01L21/768; H01L21/8246; H01L23/522; H01L27/112; H01L29/417; H01L29/78; (IPC1-7): H01L29/78; H01L21/8246; H01L27/112
Domestic Patent References:
| JP6422044A |
Attorney, Agent or Firm:
Koji Onishi