Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2954223
Kind Code:
B2
Abstract:
A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising a step or a means for automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.
Inventors:
OOE RYOICHI
YAMASHITA KOICHI
YAMASHITA KOICHI
Application Number:
JP28159288A
Publication Date:
September 27, 1999
Filing Date:
November 08, 1988
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H01L21/822; G06F17/50; H01L21/82; H01L27/04; H01L27/118; (IPC1-7): H01L21/82; H01L27/118
Domestic Patent References:
| JP5061989A | ||||
| JP60140733A | ||||
| JP6358854A | ||||
| JP59502006A |
Attorney, Agent or Firm:
Ariga Gunichiro