PURPOSE: To provide the frequency divider in which an input frequency variable range is less limited due to the restriction of a duty required for the operating clock signal of a frequency division ratio setting circuit.

CONSTITUTION: An input signal fed from a signal input terminal 11 is subject to arithmetic processing at a variable frequency divider 1 at a frequency division ratio in response to the output of a frequency division ratio setting circuit 3 and a frequency division end signal is obtained at an output terminal. A pulse width setting circuit 20 selects one of expansion amounts of the pulse width set in advance and adds its expansion amount to the frequency division end signal. The frequency division end signal to which the pulse width expansion amount is added is arithmetically processed based on frequency division ratio setting data given to a data input terminal 31 by the frequency division ratio setting circuit 3 and the result is outputted as frequency division ratio data to the variable frequency divider 1.