Title:
【発明の名称】多層神経回路網及びその回路設計方法
Document Type and Number:
Japanese Patent JP3229623
Kind Code:
B2
Abstract:
Disclosed is a multi-layer neural network and circuit design method. The multi-layer neural network receiving an m-bit input and generating an n-bit output comprises a neuron having a cascaded pair of CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as its inverted output node and an output node of the succeeding CMOS inverter as its non-inverted output node, an input layer having m neurons to receive the m-bit input, an output layer having n neurons to generate the n-bit output, at least one hidden layer provided with n neurons to transfer the input received from the input layer to the directly upper hidden layer or the output layer, an input synapse group in a matrix having each predetermined weight value to connect each output of neurons on the input layer to each neuron of the output layer and at least one hidden layer, at least one transfer synapse group in a matrix having each predetermined weight value to connect each output of neurons of the hidden layer to each neuron of its directly upper hidden layer or of the output layer, and a bias synapse group for biasing each input node of neurons of the hidden layers and the output layer.
Inventors:
Chung Ho Ho
Kim Shin Jin
Kim Shin Jin
Application Number:
JP20699091A
Publication Date:
November 19, 2001
Filing Date:
August 19, 1991
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F15/18; G06G7/60; G06N3/04; G06N3/063; G06N99/00; G11C11/54; H01L21/822; H01L27/04; (IPC1-7): G06N3/063; G06G7/60; G06N3/04; G11C11/54
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)