PURPOSE: To branch a microprogram at a high speed and to improve the performance of a data processor by varying the address of a memory decoder in accordance with the branching conditions.

CONSTITUTION: A part of the output of a microinstruction register 3 is supplied to the address input of a memory decoder 4 through a signal line 109. At the same time, the output of a subaddress register 18 is supplied to the address input of the decoder 4 through a signal line 108. While a mode where a logical arithmetic unit ALU15 delivers the contents of the 1st operad register 13 as the set data of an operation mode register 17 is stored to a word W1 of D addresses a0Wa6 of the decoder 4. While a mode where the ALU15 outputs the contents of the 2nd operand register 14 is stored to a word 2 of (128-D) addresses. Thus the read address of the decoder 4 can be varied by the value of the register 18 despite the same microinstruction. Then, it is possible to control the mode which is set to the regisrer 17.