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Title:
SIGNAL DISCRIMINATION SYSTEM
Document Type and Number:
Japanese Patent JPS5836055
Kind Code:
A
Abstract:

PURPOSE: To lighten a load on a processor by detecting data transmission is carried on in which phase modulation and frequency modulation modes by the output level of a filter which extracts the data timing signal of a received phase- modulated signal.

CONSTITUTION: When which of frequency and phase modulation modes is applied to the reception of the receiver in the figure which receives transmitted data consisting of phase-modulated low-speed data for control procedure and phase- modulated high-speed data such as a facsimile signal repeated alternately is not evident, the demodulation of a low-speed data regenerating device 1 and the timing extraction of the high-speed data of a filter 2 are carried out simultaneously. In this low-speed data processing, when the output of the filter 2 is less than a specified threshold value, the received sequence is the low-speed data and the low-speed data processing is continued. When the output of the filter 2 is greater, on the other hand, the received sequence is the high speed data, so the low-speed data processing is stopped and a high-speed data regenerating device 4 and a D-PLL3 are actuated to perform high-speed data processing.


Inventors:
UMIGAMI SHIGEYUKI
IHIRA KUNINOSUKE
TANAKA HIROYA
AONO MASA
Application Number:
JP13365981A
Publication Date:
March 02, 1983
Filing Date:
August 26, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L27/38; H04L27/14; H04L27/22; (IPC1-7): H04L27/00; H04L27/14
Attorney, Agent or Firm:
Kugoro Tamamushi



 
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