PURPOSE: To suppress unnecessary whiskers, by resetting the content of output of a register through the combination of an original signal fetched to the register respectively triggered with the rise and fall of a reference clock and the present content of the register at an ROM.
CONSTITUTION: In a CMI coding circuit, a reference clock CLK is applied to a register 31B and also a register 31A via an inverter 34, the register 31A is triggered at the rise of the CLK and the register 31B is triggered at the fall of the CLK. An original signal Din to be encoded is inputted to an ROM32 via the register 31A. 16 combinations of outputs a', b' and c' of the ROM are recirculated to the registers 31A. 31B corresponding to the combinations of address inputs x, a, b, c of the ROM32. An address (c) produces an alternating pulse train on a transmission line, outputs (b) and (a) of the registers 31A, 31B are inputted to an EOR gate 33 and a coded output Dout is produced from the gate 33. Since the registers 31A, 31B are triggered with the clocks of different phase, generation of whiskers can be prevented.
MIZUSHIMA KOUJI
OOHATA MICHINOBU
UECHI OSAMU
| JPS5570921A | 1980-05-28 | |||
| JPS5360208A | 1978-05-30 |