Title:
【発明の名称】拡散ス??トル用のプログラ?ブル整合フィル?
Document Type and Number:
Japanese Patent JPH11505983
Kind Code:
A
Abstract:
A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal are unlikely to have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips are likely to have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree. A number of AND gates inhibit the multiplexed chips from passing to some or all of the adder tree when the POWERDOWN signal is present, and pass the multiplexed chips to some or all of the adder tree when the ACTIVATION signal is present.
Inventors:
?Vidvic, ?Lin
Application Number:
JP53568296A
Publication Date:
May 25, 1999
Filing Date:
May 01, 1996
Export Citation:
Assignee:
Golden Bridge Technology Incorporated
International Classes:
H04B1/7093; H04B7/005; H04B1/708; (IPC1-7): H04B1/707
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)