Title:
【発明の名称】半導体装置の保護回路
Document Type and Number:
Japanese Patent JP2811872
Kind Code:
B2
Abstract:
There is described a protection circuit for a semiconductor device comprising power switching device chips each of which has a first and second main electrode and a control electrode for turning on and off a circuit between said first and second main electrodes (hereinafter referred to as a main circuit) in response to a control signal applied between said second main electrode and said control electrode, two of said power switching device chips being connected to form a series circuit in which said main circuits are connected in series with the same polarity, one or a plurality of said series circuits connected in parallel with the same polarity being contained in one package, and a plurality of said series circuits being connected in parallel with the same polarity, and outputting an AC voltage supply from connecting points (hereinafter referred to as midpoints) of said two power switching device chips in said series circuits by applying a DC voltage between both terminals of said parallel connected series circuits, said protection circuit being characterised by comprising temperature sensors for detecting the temperature of each or a plurality of said power switching device chips, the number of said temperature sensors being equal to or less than the total number of said power switching device chips the second main electrodes whereof are connected to said midpoints, means for generating a first alarm signal by determining that a temperature detected by any of said temperature sensors exceeds a predetermined value, said means being equipotentially coupled to a terminal point (hereinafter referred to as a point of reference potential) for said second main electrode of said power switching device chip in said series circuit, means for generating second alarm signal by determining that the current of any of said main circuits in said power switching device chips, the second electrodes whereof are connected to said point of reference potential, or a summed current of a plurality of said main circuits in these power switching device chips exceeds a predetermined value, and means for obtaining OR conditions for all of said first and second alarm signals.
Inventors:
Toshio Shigekane
Application Number:
JP4501690A
Publication Date:
October 15, 1998
Filing Date:
February 26, 1990
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H03K17/08; H02H5/04; (IPC1-7): H03K17/08
Domestic Patent References:
| JP1300568A | ||||
| JP5897716A | ||||
| JP6243210A | ||||
| JP6257539U |
Attorney, Agent or Firm:
Shoji Shinobe