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Title:
OSCILLATED FREQUENCY DIVISION CIRCUIT
Document Type and Number:
Japanese Patent JPS5945724
Kind Code:
A
Abstract:

PURPOSE: To prevent the self-oscillation of a dynamic frequency division circuit at the application of power supply, by making a logic level of a CMOS inverter functioning as an amplifier different from that of the inverter functioning as a buffer.

CONSTITUTION: A threshold voltage is changed by applying channel doping to a P-channel MOSFET80 shown in broken lines in an amplifier circuit constituting a part of an oscillating circuit. Thus, the logic level VGL1 of the oscillating circuit and the logic level VGLE of the CMOS inverter functioning as the buffer are made different from each other, allowing to prevent the transfer of an intermediate potential. Further, the similar effect is obtained by applying channel doping to an N-channel MOSFET81 to change the threshold voltage.


Inventors:
HASHIMOTO MASAMI
YAMADA ICHIROU
Application Number:
JP15693582A
Publication Date:
March 14, 1984
Filing Date:
September 09, 1982
Export Citation:
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Assignee:
SUWA SEIKOSHA KK
International Classes:
H03K21/02; H03K23/54; (IPC1-7): H03K21/02
Domestic Patent References:
JPS5315361U1978-02-08
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)



 
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