PURPOSE: To obtain a memory device having a high degree of integration with a high speed, by preventing the leakage of a writing current to the adjacent memory cell without using a large-size decoder driver, etc. to drive a word line.

CONSTITUTION: The writing voltage of a high level is impressed to a bit line BL2 from a program circuit 19 to flow a program current IP. Then a diode of a memory cell MC42 is short-circuited for execution of writing. The program IP flows into a word line WL4 from the short-circuited diode via the emitter-base junction of a pnp transistor and is absorbed by the ground through an output transistor of an NAND gate NG4 of a decoder driver 21. In this case, the odd ordinal word lines including word lines WL3 and WL5 which are adjacent to the line WL4 are all raised up to a level close to the writing state control high voltage PVCE by the function of a non-selection word line pull-up circuit 17-1. Thus the current IP never leaks via an adjacent written memory cell MC32, etc. This ensures the normal writing.