PURPOSE: To prevent increase of multiplication word length (number of times of multiplication) by possessing coefficient of low sensitivity and prescribed multiplication word length to maintain quality of signals obtained and, at the same time, processing, by addition and subtraction excepting multiplication of five times of the filter.

CONSTITUTION: Multipliers 2, 5, 6, 13 and 14 perform multiplication of coefficients a0, α1i, -α2i, -β1i, β2i and input digital signal series Xn respectively. Delay circuits 3, 4, 11 and 12 give delay time of sampling time. Shift registers 8, 16 shift output signals of delay circuits 4, 12, a shift register 9 shifts output signal of an adder, and a shift register 15 shifts output signal of the multiplier 2 by 1 bit to the right respectively. Output signals of delay circuit 3 and shift register 17 are supplied to a subtraction input terminal of an adder-subtractor 10, and output signals of shift registers 8, 9, 15 and delay circuit 11 are supplied to an addition input terminal, and a digital signal series yn-2 is outputted 17 through delay circuits 11, 12.