Title:
BASIC CELL IN MASTER SLICE SYSTEM
Document Type and Number:
Japanese Patent JPS6017930
Kind Code:
A
Abstract:
PURPOSE:To reduce the occupying area by composing not only a logic circuit such as an NAND or an NOR but also an RAM, a transmission gate circuit with less number of basic cells, thereby eliminating the production of excess transistors. CONSTITUTION:Two further p-channel transistors QP3, QP4 are aligned in parallel outside a p-channel region having two p-channel transistors QP1, QP2, and two further n-channel transistors QN3, QN4 are aligned in parallel outside an n- channel region having two n-channel transistors QN1, QN2. Therefore, when a 2- input NAND or 2-input NOR is composed, the same wirings as those using the conventional basic cell are formed, and when a transmission gate circuit or a clocked gate circuit is composed, newly added four transistors are used. Thus, when compared with the case that the conventional basic cell is used, the circuit may be formed in an area of 1/2-1/3.
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Inventors:
SATOU SHINJI
Application Number:
JP12528883A
Publication Date:
January 29, 1985
Filing Date:
July 09, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L27/092; H01L21/82; H01L21/8238; H01L27/118; (IPC1-7): H01L21/82; H01L27/04; H01L27/08
Attorney, Agent or Firm:
Shoji Kashiwaya