PURPOSE: To locate the center value of an input frequency of a PLL circuit to the center of a pull-in range by setting the phase of a phase difference output to one input of a gate signal so that an average value of the phase difference output when the relation of phase of two inputs is at random is equal to the average value when the phase difference is zero.
CONSTITUTION: When the PLL circuit is unlocked, there are 3 states; a phase difference signal OUT2 is proportional to the phase difference between the inputs A and B, and the signal OUT2 is limited respectively to periods W1 and W2. Since the said 1st state is neglected by the calculation of the average value of the signal OUT2, the probability of the 2nd and 3rd states regarded respectively as a% and (100-a)%, where a% is the duty cycle of the input A. Thus, the relation of VA=VO is established from the average value VA of the phase difference output OUT2 when the PLL circuit is unlocked and the average potential VO of the signal OUT2 when the phase difference is zero by setting properly the W1, W2 if the (a) of the input A is known, and the PLL circuit having the characteristic where the center frequency of the input frequency is the center of pull-in range is obtained even if the (a) is not 50%.
MEKI NORIO
CHIBA MITSUO
| JPS59117720A | 1984-07-07 | |||
| JPS556993A | 1980-01-18 |
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