PURPOSE: To perform simultaneously channel synchronization and frame synchronization by multiplexing plural input highways, and judging whether each highway is applied with frame synchronization, and storing an amount of phase control in a channel and information on the highway basing on the result of judgement.
CONSTITUTION: Multiplexed signals from input highways 100∼107 of a frame synchronizing circuit 10 are synchronized and adjusted in bit unit by variable delay shift registers 110∼117, series/parallel converted and selected by a multiplexer 171 and written in a speech memory 173. The address of the memory 173 is determined by the output of a control memory 181 connected to a counter 185, and 1 channel from highways 100∼107 is outputted from the memory 173. The output from the memory 173 is parallel/series converted by shift registers 140∼ 147, and the time difference of reading between highways 100∼107 is corrected. The channel synchronization and frame synchronization are performed simultaneously and the output timing of output highways OUT 0∼7 are conformed.
SHIRASU HIROTOSHI
KUWABARA HIROSHI
SUZUKI TAHEI
MORITA TAKASHI
